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| a FEATURES AC '97 2.3 COMPATIBLE FEATURES 6 DAC Channels for 5.1 Surround S/PDIF Output Integrated Stereo Headphone Amplifier Variable Rate Audio Double Rate Audio (fS = 96 kHz) Greater than 90 dB Dynamic Range 20-Bit PCM DACs Line-Level Mono "Phone" Input High Quality CD Input Selectable MIC Input with Preamp AUX and Line_In Stereo Inputs External Amplifier Power-Down Control Power Management Modes 48-Lead LQFP Package AC '97 SoundMAX Codec AD1980 (R) ENHANCED FEATURES Integrated Parametric Equalizer Stereo MIC Preamp Support Integrated PLL for System Clocking Variable Sample Rate 7 kHz to 96 kHz Jack Sense (Auto Topology Switching) Software Controlled VREF_OUT for MIC Bias Software Enabled Outputs for Jack Sharing Auto Down-Mix and Channel Spreading Modes FUNCTIONAL BLOCK DIAGRAM VREFOUT VREF VOLTAGE REFERENCE XTL_OUT XTL_IN SPDIF AD1980 MC1 MIC PREAMP G G G MC2 PHONE_IN CD_L CD_GND CD_R AUX_L AUX_R LINE_IN_L LINE_IN_R CD DIFF AMP 2CMIC CODEC CORE PCM L/R ADC RATE SPDIF TX MS PLL RECORD SELECTOR ID0 G M 16-BIT - ADC 16-BIT - ADC ID1 G M PCM LFE DAC RATE RESET LFE_OUT MZ A SPRD M G AC '97 INTERFACE 20-BIT - DAC DAC SLOT LOGIC SYNC CENTER_OUT MZ A SPRD M G 20-BIT - DAC GA M M M GA M GA M GA M GA M GA M GA M GA M M M G = GAIN A = ATTENUATION M = MUTE Z = HIGH Z PCM FRONT DAC RATE BITCLK LINE_OUT_L MZ MZ MZ A BYPASS MONO_OUT LINE_OUT_R A LOSEL EQ COEF STORAGE LOSEL SDATA_OUT EQ SDATA_IN A M M M M HPSEL G G 20-BIT - DAC 20-BIT - DAC 20-BIT - DAC 20-BIT - DAC PCM SURR DAC RATE BYPASS SURR_OUT_L/ HP_OUT_L HP M A HPSEL EQ AC '97 CONTROL REGISTERS G SURR_OUT_R/ HP_OUT_R HP M M M G A ANALOG MIXING CONTROL LOGIC EAPD JS0 JS1 EAPD REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) 2002 Analog Devices, Inc. All rights reserved. AD1980-SPECIFICATIONS STANDARD TEST CONDITIONS, UNLESS OTHERWISE NOTED DAC Test Conditions Temperature Digital Supply (DVDD) Analog Supply (AVDD) Sample Rate (fS) Input Signal Analog Output Pass Band 25C 3.3 V 5.0 V 48 kHz 1008 Hz 20 Hz to 20 kHz Calibrated -3 dB Attenuation Relative to Full Scale 0 dB Input 10 k Output Load LINE_OUT, MONO_OUT, CENTER_OUT, and LFE_OUT 32 Output Load (HP_OUT) ADC Test Conditions Calibrated 0 dB Gain Input -3.0 dB Relative to Full Scale Parameter ANALOG INPUT Input Voltage (rms Values Assume Sine Wave Input) LINE_IN, CD, AUX, PHONE_IN MIC_IN with 30 dB Preamp MIC_IN with 20 dB Preamp MIC_IN with 10 dB Preamp MIC_IN with 0 dB Gain Input Impedance* Input Capacitance* MASTER VOLUME Step Size (Line Out, Mono Out, Surround Out, Center, LFE) Output Attenuation Range Span* Mute Attenuation of 0 dB Fundamental* PROGRAMMABLE GAIN AMPLIFIER--ADC Step Size (0 dB to 22.5 dB) PGA Gain Range Span ANALOG MIXER--INPUT GAIN/AMPLIFIERS/ATTENUATORS Signal-to-Noise Ratio (SNR) CD to LINE_OUT LINE, AUX, PHONE, to LINE_OUT* MIC1 or MIC2 (Note: MIC Gain of 0 dB) to LINE_OUT* Step Size All Mixer Inputs Input Gain/Attenuation Range: All Mixer Inputs DIGITAL DECIMATION AND INTERPOLATION FILTERS* Pass Band Pass-Band Ripple Transition Band Stop Band Stop-Band Rejection Group Delay Group Delay Variation over Pass Band 0 0.4 0.6 -74 fS fS 16/fS 0 Min Typ Max Unit 1 2.83 0.032 0.089 0.1 0.283 0.316 0.894 1 2.83 20 5 1.5 46.5 7.5 V rms V p-p V rms V p-p V rms V p-p V rms V p-p V rms V p-p k pF dB dB dB dB dB 80 1.5 22.5 90 90 90 1.5 46.5 0.4 fS 0.09 0.6 fS dB dB dB dB dB Hz dB Hz Hz dB sec s -2- REV. 0 AD1980 Parameter ANALOG-TO-DIGITAL CONVERTERS Resolution Total Harmonic Distortion (THD) AVDD = 5.0 V Dynamic Range (-60 dB Input THD + N Referenced to FS, A-Weighted) AVDD = 5.0 V Signal-to-Intermodulation Distortion* (CCIF Method) ADC Crosstalk* Line Inputs (Input L, Ground R, Read R; Input R, Ground L, Read L) LINE_IN to Other Gain Error (Full-Scale Span Relative to Nominal Input Voltage) Interchannel Gain Mismatch (Difference of Gain Errors) ADC Offset Error* (0 dB Gain, HPF On) DIGITAL-TO-ANALOG CONVERTERS Resolution Total Harmonic Distortion (THD), LINE_OUT, AVDD = 5.0 V Total Harmonic Distortion (THD), HP_OUT, AVDD = 5.0 V Total Harmonic Distortion (THD), CENTER/LFE, AVDD = 5.0 V Dynamic Range (-60 dB Input THD + N Referenced to FS A-Weighted) AVDD = 5.0 V Signal-to-Intermodulation Distortion* (CCIF Method) Gain Error (Full-Scale Span Relative to Nominal Input Voltage) Interchannel Gain Mismatch (Difference of Gain Errors) DAC Crosstalk (Input L, Zero R, Read LINE_OUT_R; Input R, Zero L, Read LINE_OUT_L, 10 k Load)* Total Audible Out-of-Band Energy* (Measured from 0.6 fS to 20 kHz) ANALOG OUTPUT Full-Scale Output Voltage; LINE_OUT/MONO_OUT, CENTER_OUT, LFE_OUT Output Impedance* External Load Impedance* (LINE_OUT, CENTER_OUT/LFE_OUT, MONO_OUT) Output Capacitance* External Load Capacitance* Full-Scale Output Voltage; HP_OUT (0 dB Gain) External Load Impedance*; HP_OUT VREF VREF_OUT (VREFH = 0) VREF_OUT (VREFH = 1) VREF_OUT Current Drive Mute Click (Muted Output Minus Unmuted Midscale DAC Output) STATIC DIGITAL SPECIFICATIONS High Level Input Voltage (VIH): Digital Inputs Low Level Input Voltage (VIL) High Level Output Voltage (VOH), IOH = 2 mA Low Level Output Voltage (VOL), IOL = 2 mA Input Leakage Current Output Leakage Current POWER SUPPLY Power Supply Range; Analog (AVDD) Power Supply Range; Digital (DVDD) Power Dissipation 5 V/3.3 V Analog Supply Current 5 V (AVDD) Digital Supply Current 3.3 V (DVDD) Power Supply Rejection (100 mV p-p Signal @ 1 kHz)* (At Both Analog and Digital Supply Pins, Both ADCs and DACs) *Guaranteed but not tested. Specifications subject to change without notice. Min Typ 16 -78 82 84 -95 -90 Max Unit Bits dB dB dB -90 -85 10 0.5 10 dB dB % dB mV Bits dB dB dB dB 20 -90 -73 -82.5 90 88 10 0.7 -80 -40 dB % dB dB dB 1 2.83 800 10 15 100 1 32 2.05 2.25 2.25 3.65 5 0.65 0.9 -10 -10 4.75 3.15 563 70 53 40 DVDD 0.35 DVDD 0.1 DVDD +10 +10 5.25 3.45 DVDD 2.45 V rms V p-p k pF pF V rms V V V mA mV V V V V A A V V mW mA mA dB 5 REV. 0 -3- AD1980 Parameter POWER-DOWN STATES Fully Active ADC FRONT DAC SURROUND DAC CENTER/LFE DAC ADC + ALL DACs Mixer ADC + Mixer ALL DACs + Mixer ADC + ALL DACs + Mixer Standby Headphone Standby 2 PR[K:I]1 000 000 000 010 101 111 000 000 111 111 111 000 PR[6:0]1 000 0000 000 0001 000 0010 000 0000 000 0000 000 0011 000 0100 000 0101 000 0110 000 0111 011 1111 100 0000 DVDD Typ 53 44 46 46 46 12 52 45 31 12 0 52 AVDD Typ 70 66 61 61 61 33 44 39 14 8 0 65 Unit mA mA mA mA mA mA mA mA mA mA mA mA NOTES 1 PR bits are controlled in Reg. 2Ah and 26h 2 Values presented with V REFOUT loaded. Specifications subject to change without notice. Parameter CLOCK SPECIFICATIONS Input Clock Frequency (XTAL Mode or Clock Oscillator) Input Clock Frequency (Reference Clock Mode) Input Clock Frequency (USB Clock Mode) Recommended Clock Duty Cycle Guaranteed but not tested. Specifications subject to change without notice. * Min * Typ 24.576 14.31818 48.000 50 Max Unit MHz MHz MHz % 40 60 TIMING PARAMETERS (Guaranteed over Operating Temperature Range) Parameter RESET Active Low Pulsewidth RESET Inactive to BIT_CLK Startup Delay SYNC Active High Pulsewidth SYNC Low Pulsewidth SYNC Inactive to BIT_CLK Startup Delay BIT_CLK Frequency BIT_CLK Frequency Accuracy BIT_CLK Period BIT_CLK Output Jitter1, 2 BIT_CLK High Pulsewidth BIT_CLK Low Pulsewidth SYNC Frequency SYNC Period Setup to Falling Edge of BIT_CLK Hold from Falling Edge of BIT_CLK BIT_CLK Rise Time BIT_CLK Fall Time SYNC Rise Time SYNC Fall Time SDATA_IN Rise Time SDATA_IN Fall Time SDATA_OUT Rise Time SDATA_OUT Fall Time End of Slot 2 to BIT_CLK, SDATA_IN Low Setup to RESET Inactive (SYNC, SDATA_OUT) Rising Edge of RESET to Hi-Z Delay Propagation Delay RESET Rise Time Output Valid Delay from BIT_CLK Rising NOTES 1 Guaranteed but not tested. 2 Output jitter directly dependent on crystal input jitter. Specifications subject to change without notice. Symbol tRST_LOW tRST2CLK tSYNC_HIGH tSYNC_LOW tSYNC2CLK tCLK_PERIOD tCLK_HIGH tCLK_LOW tSYNC_PERIOD tSETUP tHOLD tRISECLK tFALLCLK tRISESYNC tFALLSYNC tRISEDIN tFALLDIN tRISEDOUT tFALLDOUT tS2_PDOWN tSETUP2RST tOFF Min 162.8 Typ 1.0 Max 400,000 Unit s ns s s ns MHz ppm ns ps ns ns kHz s ns ns ns ns ns ns ns ns ns ns s ns ns ns ns ns 1.3 19.5 162.8 12.288 1.0 81.4 750 40 39.7 48.0 20.8 4 3 2 2 2 2 2 2 2 2 0 15 4 4 4 4 4 4 4 4 6 6 6 6 6 6 6 6 1.0 25 15 50 15 41.7 41.4 -4- REV. 0 AD1980 tRST2CLK tRST_LOW RESET tTRI2ACTV BIT_CLK tTRI2ACTV SDATA_IN Figure 1. Cold Reset Timing (Codec is Supplying the Bit_CLK Signal) tSYNC_HIGH SYNC tSYNC2CLK BIT_CLK Figure 2. Warm Reset Timing tCLK_LOW SYNC BIT_CLK SLOT 1 SLOT 2 tCLK_HIGH tCLK_PERIOD BIT_CLK SDATA_OUT tSYNC_LOW SYNC WRITE TO 0 26 DATA PR4 tS2_PDOWN SDATA_IN tSYNC_HIGH tSYNC_PERIOD BIT_CLK NOT TO SCALE Figure 5. AC-Link Low Power Mode Timing tCO tSETUP Figure 3. Clock Timing BIT_CLK tRISECLK tFALLCLK BIT_CL VIH VIL SYNC SDATA_O tRISESYNC tFALLSYNC SDATA_I SYN VOH VOL SDATA_IN tHOLD tRISEDIN tFALLDIN Figure 6. AC-Link Low Power Mode Timing RESET SDATA_OUT tRISEDOUT tFALLDOUT SDATA_OUT Figure 4. Signal Rise and Fall Times tSETUP2RST SDATA_IN, BIT_CLK, EAPD, SPDIF_OUT AND DIGITAL I/O Hi-Z tOFF Figure 7. ATE Test Mode REV. 0 -5- AD1980 ABSOLUTE MAXIMUM RATINGS* ENVIRONMENTAL CONDITIONS* Parameter Power Supplies Digital (DVDD) Analog (AVDD) Input Current (Except Supply Pins) Analog Input Voltage (Signal Pins) Digital Input Voltage (Signal Pins) Ambient Temperature (Operating) Storage Temperature Min -0.3 -0.3 -0.3 -0.3 0 -65 Max +3.6 +6.0 10.0 AVDD + 0.3 DVDD + 0.3 70 +150 Unit V V mA V V C C Ambient Temperature Rating TCASE = Case Temperature in C PD = Power Dissipation in W JA = Thermal Resistance (Junction-to-Ambient) JC = Thermal Resistance (Junction-to-Case) Package LQFP JA JC 50.1C/W 17.8C/W *Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. *All measurements per EIA/JESD51 with 2S2P test board per EIA/JESD51-7. ORDERING GUIDE Model AD1980JST Temperature Range 0C to 70C Package Description 48-Lead LQFP Package Option* ST-48 *ST = Low Profile Quad Flatpack CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD1980 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. PIN CONFIGURATION 48-Lead LQFP SURR_OUT_R/HP_OUT_R SURR_OUT_L/HP_OUT_L 48 47 46 45 44 43 42 41 40 39 38 37 DVDD1 MONO_OUT 36 LINE_OUT_R (FRONT_R) 35 LINE_OUT_L (FRONT_L) 34 AVDD4 33 AVSS4 32 LFE_OUT 31 CENTER_OUT 30 AFILT2 29 AFILT1 28 VREFOUT 27 VREF 26 AVSS1 25 AVDD1 24 AVDD3 AVSS3 1 XTL_IN 2 XTL_OUT DVSS1 SDATA_OUT BIT_CLK DVSS2 3 4 5 6 7 AD1980 TOP VIEW (Not to Scale) SDATA_IN 8 DVDD2 9 SYNC 10 RESET 11 NC 12 13 14 15 16 17 18 19 20 21 22 23 AVSS2 SPDIF EAPD ID1 ID0 NC AVDD2 LINE_IN_L PHONE_IN NC = NO CONNECT CD_GND_REF -6- LINE_IN_R AUX_R CD_R MC1 AUX_L CD_L MC2 JS1 JS0 REV. 0 AD1980 PIN FUNCTION DESCRIPTIONS Pin Number 2 3 5 6 8 10 11 48 45 46 47 17 16 13 14 15 18 19 20 21 22 23 24 31 32 35 36 37 39 41 FILTER/REFERENCE 27 28 29 30 Mnemonic XTL_IN XTL_OUT SDATA_OUT BIT_ CLK SDATA_IN SYNC RESET SPDIF ID0 ID1 EAPD JS0 JS1 PHONE_IN AUX_L AUX_R CD_L CD_GND_REF CD_ R MIC1 MIC2 LINE_IN_L LINE_IN_R CENTER_OUT LFE_OUT LINE_OUT_L LINE_OUT_R MONO_OUT SURR_OUT_L/HP_OUT_L SURR_OUT_R/HP_OUT_R VREF VREFOUT AFILT1 AFILT2 I/O I O I O/I O I I O I I O I I I I I I I I I I I I O O O O O O O O O O O Function Crystal Input (24.576 MHz) or External Clock In (24.576 MHz, 14.31818 MHz or 48000 MHz) Crystal Output AC-Link Serial Data Output. AD1980 Input Stream. AC-Link Bit Clock. 12.288 MHz serial data clock. (Input pin, for Secondary mode only.) AC-Link Serial Data Input. AD1980 Output Stream. AC-Link Frame Sync AC-Link Reset. AD1980 Master H/W Reset. SPDIF Output Chip Select Input 0 (Active Low). This pin can also be used as the chain input from a secondary Codec. Chip Select Input 1 (Active Low) EAPD Output Jack Sense 0 Input Jack Sense 1 Input Monaural Line-Level Input Auxiliary Input, Left Channel Auxiliary Input, Right Channel CD Audio Left Channel CD Audio Analog Ground Reference for Differential CD Input CD Audio Right Channel Microphone #1 Input (Left Channel when 2-Channel Mode Selected) Microphone #2 Input (Right Channel when 2-Channel Mode Selected) Line-In Left Channel Line-In Right Channel Center Channel Output Low Frequency Enhanced Output Line-Out (Front) Left Channel Line-Out (Front) Right Channel Monaural Output to Telephone Subsystem Speakerphone Surround or Front Headphone Left Channel Output Surround or Front Headphone Right Channel Output Voltage Reference Filter Voltage Reference Output 5 mA Drive (intended for MIC bias) Antialiasing Filter Capacitor--ADC Right Channel Antialiasing Filter Capacitor--ADC Left Channel DIGITAL INPUT/OUTPUT CHIP SELECTS/CLOCK STRAPPING JACK SENSE AND EAPD ANALOG INPUT/OUTPUT REV. 0 -7- AD1980 Pin Number Mnemonic I/O I I I I I I I I I I I I Function Digital VDD 3.3 V Digital GND Digital GND Digital VDD 3.3 V Analog VDD 5.0 V Analog GND Analog GND Analog VDD 5.0 V Analog VDD 5.0 V Analog GND Analog VDD 5.0 V Analog GND No Connect No Connect POWER AND GROUND SIGNALS 1 DVDD1 4 DVSS1 7 DVSS2 9 DVDD2 25 AVDD1 26 AVSS1 33 AVSS4 34 AVDD4 38 AVDD2 40 AVSS2 43 AVDD3 44 AVSS3 NO CONNECTS 12 42 NC NC -8- REV. 0 AD1980 Indexed Control Registers Reg Name 00h Reset 02h Master Volume 04h Headphone Volume 06h Mono Volume 0Ch Phone Volume 0Eh Mic Volume 10h Line In Volume 12h CD Volume 16h AUX Volume 18h PCM Out Vol 1Ah Record Select 1Ch Record Gain D15 X MM HPM MVM PHM MCM LVM CVM AVM OM X IM D14 SE4 X X X X X X X X X X X X X D13 SE3 LMV5 LHV5 X X X X X X X X X X X D12 SE2 LMV4 LHV4 X X X LLV4 LCV4 LAV4 LOV4 X X X X D11 SE1 LMV3 LHV3 X X X LLV3 LCV3 LAV3 LOV3 X LIM3 DRSS1 I0 D10 SE0 LMV2 LHV2 X X X LLV2 LCV2 LAV2 LOV2 LS2 LIM2 DRSS0 X D9 ID9 D8 ID8 D7 ID7 D6 ID6 D5 ID5 D4 ID4 D3 ID3 D2 ID2 D1 ID1 D0 ID0 Default 0090h 8000h 8000h 8000h 8008h 8008h 8808h 8808h 8808h 8808h 0000h 8000h 0000h xxxx LMV1 LMV0 LHV1 X X X LLV1 LCV1 LAV1 LOV1 LS1 LIM1 X X LHV0 X X X LLV0 LCV0 LAV0 LOV0 LS0 LIM0 MS X MMRM* X HPRM* X X X LVRM* X X X M20 X RMV5 RMV4 RMV3 RMV2 RMV1 RMV0 RHV5 MV5 X X X X X X X X X X RHV4 MV4 PHV4 RHV3 MV2 PHV3 RHV2 MV2 PHV2 RHV1 MV1 PHV1 RHV0 MV0 PHV0 MCV4 MCV3 MCV2 MCV1 MCV0 RLV4 RCV4 RAV4 ROV4 X X X X RLV3 RCV3 RAV3 ROV3 X RIM3 X PG3 RLV2 RCV2 RAV2 ROV2 RS2 RIM2 X PG2 RLV1 RCV1 RAV1 ROV1 RS1 RIM1 X PG1 RLV0 RCV0 RAV0 ROV0 RS0 RIM0 X PG0 CDRM* X AVRM* X OMRM* X X IMRM LPBK X X X X X 20h General Purpose X 24h Audio Int. and Paging 26h Power-Down Ctrl/Stat 28h Ext'd Audio ID 2Ah Ext'd Audio Stat/Ctrl 2Ch PCM Front DAC Rate 2Eh PCM Surr DAC Rate 30h PCM C/LFE DAC Rate 32h PCM ADC Rate 36h Center/LFE Volume I4 EAPD PR6 PR5 PR4 PR3 PR2 PR1 PR0 X X X X REF ANL DAC ADC 0NA ID1 ID0 X PRK X PRJ REV1 PRI REV0 SPCV AMAP LDAC X SDAC CDAC DSA1 DSA0 X SPDIF DRA VRAS x3C7h 0xx0h VFORCE X ELDAC ESDAC ECDAC SPSA1 SPSA0 X ESPDIF EDRA EVRA SRF15 SRF14 SRF13 SRF12 SRF11 SRF10 SRF9 SRF8 SRF7 SRF6 SRF5 SRF4 SRF3 SRF2 SRF1 SRF0 BB80h SRS15 SRS14 SRS13 SRS12 SRS11 SRS10 SRS9 SRS8 SRS7 SRS6 SRS5 SRS4 SRS3 SRS2 SRS1 SRS0 BB80h SRCL15 SRCL14 SRCL13 SRCL12 SRCL11 SRCL10 SRCL9 SRCL8 SRCL7 SRCL6 SRCL5 SRCL4 SRCL3 SRCL2 SRCL1 SRCL0 BB80h SRA15 SRA14 SRA13 SRA13 SRA11 SRA10 SRA9 SRA8 SRA7 SRA6 SRA5 SRA4 SRA3 SRA2 SRA1 SRA0 BB80h LM X LFE5 LFE4 LFE3 LFE2 LFE1 LFE0 CM X CNT5 CNT4 CNT3 CNT2 CNT1 CNT0 8080h 38h Surround Volume MUTE_L X 3Ah SPDIF Control 60h EQ CTRL 62h EQ DATA 72h JACK SENSE V EQM CFD15 JS1 SPRD X X CFD14 JS1 DMX LSR5 SPSR1 X CFD13 JS0 DMX LSR4 SPSR0 X CFD12 JS MT2 LSR3 L X CFD11 JS MT1 LSR2 CC6 X CFD10 JS MT0 LSR1 CC5 X CFD9 JS1 EQB X LSR0 CC4 X CFD8 JS0 EQB CHEN MUTE_R X CC3 SYM CFD7 JS1 TMR X CC2 CHS CFD6 JS0 TMR LBK1 RSR5 CC1 BCA5 CFD5 JS1 MD LBK0 RSR4 CC0 BCA4 CFD4 JS0 MD INTS RSR3 PRE BCA3 CFD3 JS1 ST X RSR2 RSR1 RSR0 PRO BCA0 CFD0 JS0 INT SPLNK 8080h 2000h 8080h 0000h 0000h COPY /AUD BCA2 CFD2 JS0 ST SPAL BCA1 CFD1 JS1 INT SPDZ 74h Serial Configuration 76h Misc Control Bits 7Ch Vendor ID1 7Eh Vendor ID2 SLOT 16 REGM2 REGM1 REGM0 REGM3 DRF 1001h DACZ AC97NC MSPLT LODIS CLDIS HPSEL DMIX1 DMIX0 SPRD 2CMIC LOSEL SRU VREFH VREFD MBG1 MBG0 0000h F7 T7 F6 T6 F5 T5 F4 T4 F3 T3 F2 T2 F1 T1 F0 T0 S7 REV7 S6 REV6 S5 REV5 S4 REV4 S3 REV3 S2 REV2 S1 REV1 S0 REV0 4144h 5370h NOTES All registers not shown and bits containing an X are assumed to be reserved. Odd register addresses are aliased to the next lower even address. Reserved registers should not be written to. Zeros should be written to reserved bits. *For AC '97 compatibility, Bit D7 is only available by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right channels. If MSPLT is not set, Bit D7 has no effect. REV. 0 -9- AD1980 Reset Register (Index 00h) Reg No. 00h Name Reset D15 X D14 SE4 D13 SE3 D12 SE2 D11 SE1 D10 SE0 D9 ID9 D8 ID8 D7 ID7 D6 ID6 D5 ID5 D4 ID4 D3 ID3 D2 ID2 D1 ID1 D0 ID0 Default 0090h NOTES All registers not shown and bits containing an X are assumed to be reserved. Writing any value to this register performs a register reset, which causes all registers to revert to their default values (except 74h, which forces the serial configuration). Reading this register returns the ID code of the part and a code for the type of 3D Stereo Enhancement. ID[9:0] Identify Capability. The ID decodes the capabilities of AD1980 based on the following: Bit = 1 ID0 ID1 ID2 ID3 ID4 ID5 ID6 ID7 ID8 ID9 Function Dedicated Mic PCM In Channel Modem Line Codec Support Bass and Treble Control Simulated Stereo (Mono to Stereo) Headphone Out Support Loudness (Bass Boost) Support 18-Bit DAC Resolution 20-Bit DAC Resolution 18-Bit ADC Resolution 20-Bit ADC Resolution AD1980 0 0 0 0 1 0 0 1 0 0 SE[4:0] Stereo Enhancement. The AD1980 does not provide hardware 3D stereo enhancement. (All bits are zeros.) Master Volume Register (Index 02h) Reg No. 02h Name D15 D14 D131 X D12 D11 D10 D9 D8 D7 2 D6 D51 D4 D3 D2 D1 D0 Default Master MM Volume LMV5 LMV4 LMV3 LMV2 LMV1 LMV0 MMRM X RMV5 RMV4 RMV3 RMV2 RMV1 RMV0 8000h NOTES 1 Refer to Table I for examples. This register controls the Line_Out volume controls for both stereo channels and mute bit. Each volume subregister contains five bits, generating 32 volume levels with 31 steps of 1.5 dB each. Because AC '97 defines 6-bit volume registers, to maintain compatibility whenever the D5 or D13 bits are set to "1," their respective lower five volume bits are automatically set to "1" by the codec logic. On readback, all lower five bits will read "1s" whenever these bits are set to "1." 2 For AC '97 compatibility, Bit D7 is available only by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right channels. If MSPLT is not set, bit D7 has no effect. All registers not shown and bits containing an X are assumed to be reserved. Note that depending on the state of the AC97NC bit in Register 0x76, this register has the following additional functionality: For AC97NC = 0, the register controls the Line_out output Attenuators only. For AC97NC = 1, the register controls the Line_out, Center, and LFE output Attenuators. RMV[5:0] RM LMV[5:0] MM Right Master Volume Control. The least significant bit represents 1.5 dB. This register controls the output from 0 dB to a maximum attenuation of 46.5 dB. Right Channel Mute. Once enabled by the MSPLT bit in Register 76h, this bit mutes the right channel separately from the MM bit. Otherwise this bit will always read "0" and will have no effect when set to "1." Left Master Volume Control. The least significant bit represents 1.5 dB. This register controls the output from 0 dB to a maximum attenuation of 46.5 dB. Headphones Volume Mute. When this bit is set to "1," both the left and the right channels are muted, unless the MSPLT bit in Register 76h is set to "1." -10- REV. 0 AD1980 Headphones Volume Register (Index 04h) Reg No. Name 04h Headphones Volume D15 HPM D14 X D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default LHV5 LHV4 LHV3 LHV2 LHV1 LHV0 HPRM* X RHV5 RHV4 RHV3 RHV2 RHV1 RHV0 8000h *For AC '97 compatibility, Bit D7 is available only by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right channels. If MSPLT is not set, Bit D7 has no effect. Table I. Volume Settings for Master and Headphone Reg. 76h MSPLT* D15 WRITE 0 0 0 0 0 1 1 1 0 0 0 0 1 0 1 1 00 0000 00 1111 01 1111 1x xxxx xx xxxx 1x xxxx xx xxxx xx xxxx Control Bits Master Volume (02h) and Headphone Volume (04h) Left Channel Volume D[13:8] READBACK Function 00 0000 00 1111 01 1111 01 1111 xx xxxx 01 1111 xx xxxx xx xxxx 0 dB Gain -22.5 dB Gain -46.5 dB Gain -46.5 dB Gain - dB Gain, Muted -46.5 dB Gain - dB Gain, Left only Muted - dB Gain, Left Muted D7* x x x x x 1 0 1 Right Channel Volume D[5:0] WRITE READBACK 00 0000 00 1111 01 1111 1x xxxx xx xxxx xx xxxx xx xxxx xx xxxx 00 0000 00 1111 01 1111 01 1111 xx xxxx xx xxxx xx xxxx xx xxxx Function 0 dB Gain -22.5 dB Gain -46.5 dB Gain -46.5 dB Gain - dB Gain, Muted - dB Gain, only Right Muted -46.5 dB Gain - dB Gain, Right Muted *For AC '97 compatibility, Bit D7 is available only by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right channels. If MSPLT is not set, Bit D7 has no effect. x in the above table is "don't care." Mono Volume Register (Index 06h) Reg No. Name 06h D15 D14 D13 X X D12 X D11 X D10 X D9 X D8 X D7 X D6 X D5* MV5 D4 MV4 D3 MV3 D2 MV2 D1 MV1 D0 MV0 Default 8000h Mono Volume MVM *Refer to Table II for examples. This register controls the Mono output volume and mute bit. The volume register contains five bits, generating 32 volume levels with 31 steps of 1.5 dB each. Because AC '97 defines 6-bit volume registers, to maintain compatibility, whenever the D5 bit is set to "1," their respective lower five volume bits are automatically set to "1" by the codec logic. On readback, all lower five bits will read "1s" whenever this bit is set to "1." All registers not shown and bits containing an X are assumed to be reserved. MV[5:0] MVM Mono Volume Control. The least significant bit represents 1.5 dB. This register controls the output from 0 dB to a maximum attenuation of 46.5 dB. Mono Volume Mute. When this bit is set to "1," the channel is muted. Table II. Volume Settings for Mono Control Bits D[4:0] for Mono (06h) D15 0 0 0 1 WRITE 0 0000 0 1111 1 1111 x xxxx READBACK 0 0000 0 1111 1 1111 x xxxx Function 0 dB Gain -22.5 dB Gain -46.5 dB Gain - dB Gain, Muted x in the above table is a wild card and has no effect on the value. REV. 0 -11- AD1980 Phone_in Volume Register (Index 0Ch) Reg No. Name D15 D14 D13 X D12 X D11 X D10 X D9 X D8 X D7 X D6 X D5 X D4 PHV4 D3 PHV3 D2 PHV2 D1 D0 Default 8008h 0Ch Phone_in Volume PHM X PHV1 PHV0 All registers not shown and bits containing an X are assumed to be reserved. Refer to Table III for examples. PHV[4:0] PHM Phone Volume. Allows setting the Phone Volume attenuator in 32 volume levels with 31 steps of 1.5 dB each. The LSB represents 1.5 dB, and the gain range is +12 dB to -34.5 dB. The default value is 0 dB, with the mute bit enabled. Phone Mute. When this bit is set to "1," the Phone channel is muted. MIC Volume Register (Index 0Eh) Reg No. Name 0Eh MIC Volume D15 MCM D14 D13 X X D12 X D11 X D10 X D9 X D8 X D7 X D6 M20 D5 X D4 MCV4 D3 MCV3 D2 MCV2 D1 D0 Default MCV1 MCV0 8008h All registers not shown, and bits containing an X are assumed to be reserved. Refer to Table III for examples. MCV[4:0] M20 MIC Volume Gain. Allows setting the MIC Volume attenuator in 32 volume levels. The LSB represents 1.5 dB, and the gain range is +12 dB to -34.5 dB. The default value is 0 dB, with mute enabled. MIC Gain Boost. This bit allows setting additional MIC gain to increase the microphone sensitivity. The nominal gain boost by default is 20 dB, however, Bits D0 and D1 (MBG[1:0]) on the miscellaneous control bits register (76h) allow changing the gain boost to 10 dB or 30 dB, if necessary. 0 = Disabled; Gain = 0 dB 1 = Enabled; Default Gain = 20 dB (see Register 76h, Bits D0, D1) MIC Mute. When this bit is set to "1," the channel is muted. Table III. Volume Settings for Phone and MIC MCM Control Bits D[4:0] Phone (0Ch) and MIC (0Eh) D15 0 0 0 1 WRITE 0 0000 0 1000 1 1111 x xxxx READBACK 0 0000 0 1000 1 1111 x xxxx Function 12 dB Gain 0 dB Gain -34.5 dB Gain - dB Gain, Muted x in the above table is a wild card, and has no effect on the value. -12- REV. 0 AD1980 Line-In Volume Register (Index 10h) Reg No. Name D15 D14 D13 D12 X X D11 D10 LLV2 D9 D8 D7 D6 D5 D4 X D3 D2 RLV2 D1 D0 Default 10h Line-In Volume LVM LLV4 LLV3 LLV1 LLV0 LVRM* X RLV4 RLV3 RLV1 RLV0 8808h *For AC '97 compatibility, Bit D7 is available only by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right channels. If MSPLT is not set, the Bit D7 has no effect. All registers not shown and bits containing an X are assumed to be reserved. Refer to Table IV for examples. RLV[4:0] RM LLV[4:0] LVM Right Line-In Volume. Allows setting the Line-In Right channel attenuator in 32 volume levels with 31 steps of 1.5 dB each. The LSB represents 1.5 dB, and the range is +12 dB to -34.d dB. The default value is 0 dB, mute enabled. Right Channel Mute. Once enabled by the MSPLT bit in Register 76h, this bit mutes the right channel separately from the LIM bit. Otherwise, this bit will always read "0" and will have no effect when set to "1." Left Line-In Volume. Allows setting the Line-In left channel attenuator in 32 volume levels with 31 steps of 1.5 dB each. The LSB represents 1.5 dB, and the range is +12 dB to -34.5 dB. The default value is 0 dB, mute enabled. Line-In Mute. When this bit is set to "1," both the left and the right channels are muted, unless the MSPLT bit in Register 76h is set to "1," in which case this mute bit will only affect the left channel. CD Volume Register (Index 12h) Reg No. Name 12h CD Volume D15 D14 D13 D12 X D11 D10 D9 D8 D7 D6 D5 D4 X D3 D2 D1 D0 Default CVM X LCV4 LCV3 LCV2 LCV1 LCV0 CDRM* X RCV4 RCV3 RCV2 RCV1 RCV0 8808h *For AC '97 compatibility, Bit D7 is available only by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right channels. If MSPLT is not set, the Bit D7 has no effect. All registers not shown and bits containing an X are assumed to be reserved. Refer to Table IV for examples. RCV[4:0] RM LCV[4:0] CVM Right CD Volume. Allows setting the CD right channel attenuator in 32 volume levels with 31 steps of 1.5 dB each. The LSB represents 1.5 dB, and the range is +12 dB to -34.5 dB. The default value is 0 dB, mute enabled. Right Channel Mute. Once enabled by the MSPLT bit in Register 76h, this bit mutes the Right channel separately from the CVM bit. Otherwise this bit will always read "0" and will have no effect when set to "1." Left CD Volume. Allows setting the CD left channel attenuator in 32 volume levels with 31 steps of 1.5 dB each. The LSB represents 1.5 dB, and the range is +12 dB to -24.5 dB. The default value is 0 dB, mute enabled. CD Volume Mute. When this bit is set to "1," both the left and the right channels are muted, unless the MSPLT bit in Register 76h is set to "1," in which case this mute bit will affect only the left channel. AUX Volume Register (Index 16h) Reg No. Name 16h AUX Volume D15 AVM D14 D13 D12 X X D11 D10 D9 D8 D7 D6 D5 X D4 D3 D2 D1 D0 Default LAV4 LAV3 LAV2 LAV1 LAV0 AVRM* X RAV4 RAV3 RAV2 RAV1 RAV0 8808h *For AC '97 compatibility, Bit D7 is only available by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right channels. If MSPLT is not set, Bit D7 has no effect. All registers not shown and bits containing an X are assumed to be reserved. Refer to Table IV for examples. RAV[4:0] RM LAV[4:0] AVM Right AUX Volume. Allows setting the AUX right channel attenuator in 32 volume levels with 31 steps of 1.5 dB each. The LSB represents 1.5 dB, and the range is +12 dB to -34.5 dB. The default value is 0 dB, mute enabled. Right Channel Mute. Once enabled by the MSPLT bit in Register 76h, this bit mutes the right channel separately from the AVM bit. Otherwise, this bit will always read "0" and will have no affect when set to "1." Left PCM Out Volume. Allows setting the PCM left channel attenuator in 32 volume levels. The LSB represents 1.5 dB, and the range is +12 dB to -34.5 dB. The default value is 0 dB, mute enabled. PCM Out Volume Mute. When this bit is set to "1," both the left and the right channels are muted, unless the MSPLT bit in Register 76h is set to "1," in which case this mute bit will affect only the left channel. REV. 0 -13- AD1980 PCM-Out Volume Register (Index 18h) Reg No. Name D15 D14 D13 D12 X D11 D10 D9 D8 D7 D6 D5 D4 X ROV4 D3 ROV3 D2 D1 D0 Default 18h PCM Out Volume OM X LOV4 LOV3 LOV2 LOV1 LOV0 OMRM* X ROV2 ROV1 ROV0 8808h *For AC '97 compatibility, Bit D7 is available only by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right channels. If MSPLT is not set, Bit D7 has no effect. All registers not shown and bits containing an X are assumed to be reserved. Refer to Table IV for examples. Note that depending on the state of the AC97NC bit in Register 76h, this register has the following additional functionality: For AC87NC = 0, the register also controls the Surround, Center, and LFE DAC Gain/Attenuators. For AC97NC = 1, the register controls the PCM Out Volume only. ROV[4:0] RM LOV[4:0] OM Right PCM Out Volume. Allows setting the PCM right channel attenuator in 32 volume levels. The LSB represents 1.5 dB, and the gain range is +12 dB to -34.5 dB. The default value is 0 dB, mute enabled. Right Channel Mute. Once enabled by the MSPLT bit in Register 76h, this bit mutes the right channel separately from the AVM bit. Otherwise, this bit will always read "0" and will have no affect when set to "1." Left PCM Out Volume. Allows setting the PCM left channel attenuator in 32 volume levels. The LSB represents 1.5 dB, and the range is +12 dB to -34.5 dB. The default value is 0 dB, mute enabled. PCM Out Volume Mute. When this bit is set to "1," both the left and the right channels are muted, unless the MSPLT bit in Register 76h is set to "1," in which case this mute bit will affect only the left channel. Table IV. Volume Settings for Line-In, CD Volume, AUX, and PCM-Out Reg. 76h Control Bits Line-In (10h), CD (12h), AUX (16h) and PCM-Out (18h) Left Channel Volume D[12:8] Right Channel Volume D[4:0] D7* WRITE x x x x 1 0 0000 0 1000 1 1111 x xxxx x xxxx 1 1111 x xxxx READBACK Function 0 0000 0 1000 1 1111 x xxxx x xxxx 1 1111 x xxxx 12 dB Gain 0 dB Gain -34.5 dB Gain - dB Gain, Muted - dB Gain, Right Only Muted -34.5 dB Gain - dB Gain, Right Muted MSPLT* D15 WRITE READBACK Function 0 0 0 0 1 1 1 0 0 0 1 0 1 1 0 0000 0 1000 1 1111 x xxxx 1 1111 x xxxx x xxxx 0 0000 0 1000 1 1111 x xxxx 1 1111 x xxxx x xxxx 12 dB Gain 0 dB Gain -34.5 dB Gain - dB Gain, Muted -34.5 dB Gain - dB Gain, 0 Left Only Muted - dB Gain, Left Muted 1 *For AC '97 compatibility, Bit D7 is only available by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right channels. If MSPLT is not set, RM Bit has no effect. x in the above table is "don't care." Record Select Control Register (Index 1Ah) Reg No. Name 1Ah Record Select D15 X D14 X D13 X D12 X D11 X D10 LS2 D9 LS1 D8 LS0 D7 X D6 X D5 X D4 X D3 X D2 RS2 D1 RS1 D0 RS0 Default 0000h All registers not shown and bits containing an X are assumed to be reserved. Refer to Table V for examples. Used to select the record source, independently for the right and left channels. For single MIC recording, see MS bit (Register 20h) for MIC1 and MIC2 input selection. For dual MIC recording, see 2CMIC bit (Register 76h) to enable simultaneous recording into the left and the right channels. The default value is 0000h, which corresponds to MIC input for both channels. RS [2:0] LS [2:0] Right Record Select Left Record Select -14- REV. 0 AD1980 Table V. Settings for Record Select Control LS [10:8] 000 001 010 011 100 101 110 111 Left Record Source MIC CD_L Muted AUX_L LINE_IN_L Stereo Mix (L) Mono Mix PHONE_IN RS [2:0] 000 001 010 011 100 101 110 111 Right Record Source MIC CD_R Muted AUX_R LINE_IN_R Stereo Mix (R) Mono Mix PHONE_IN Record Gain Register (Index 1Ch) Reg No. Name 1Ch Record Gain D15 IM D14 X D13 X D12 X D11 LIM3 D10 LIM2 D9 LIM1 D8 D7 D6 D5 X D4 D3 X RIM3 D2 D1 D0 Default LIM0 IMRM* X RIM2 RIM1 RIM0 8000h *For AC '97 compatibility, Bit D7 is available only by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right channels. If MSPLT is not set, Bit D7 has no effect. All registers not shown, and bits containing an X are assumed to be reserved. Refer to Table VI for examples. RIM[3:0] RM LIM[3:0] IM Right Input Mixer Gain Control. Each LSB represents 1.5 dB, 0000 = 0 dB, and the gain range is 0 dB to 22.5 dB. Right Channel Mute. Once enabled by the MSPLT bit in Register 76h, this bit mutes the right channel separately from the IM bit. Otherwise, this bit will always read "0" and will have no effect when set to "1." Left Input Mixer Gain Control. Each LSB represents 1.5 dB, 0000 = 0 dB, and the gain range is 0 dB to 22.5 dB. Input Mute. When this bit is set to "1," both the left and the right channels are muted, unless the MSPLT bit in Register 76h is set to "1," in which case this mute bit will affect only the left channel. Table VI. Settings for Record Gain Register Reg. 76h Control Bits Record Gain (1Ch) Left Channel Input Mixer D[11:8] Right Channel Input Mixer D[3:0] D7* x x x 1 0 1 WRITE 1111 0000 xxxx xxxx 1111 xxxx READBACK Function 1111 0000 xxxx xxxx 1111 xxxx 22.5 dB Gain 0 dB Gain - dB Gain, Muted - dB Gain, Right Only Muted 22.5 dB Gain - dB Gain, Right Muted MSPLT* D15 WRITE 0 0 0 1 1 1 0 0 1 0 1 1 1111 0000 xxxx 1111 xxxx xxxx READBACK 1111 0000 xxxx 1111 xxxx xxxx Function 22.5 dB Gain 0 dB Gain - dB Gain, Muted 22.5 dB Gain - dB Gain, Left Only Muted - dB Gain, Left Muted *For AC '97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right channels. If MSPLT is not set, Bit D7 has no effect. x is "don't care." REV. 0 -15- AD1980 General-Purpose Register (Index 20h) Reg No. Name 20h D15 D14 X D13 X D12 D11 X D10 D9 X D8 MS D7 LPBK D6 X D5 X D4 X D3 X D2 X D1 X D0 X Default 0000h General-Purpose X DRSS1 DRSS0 This register should be read before writing to generate a mask for only the bit(s) that need to be changed. All registers not shown and bits containing an X are assumed to be reserved. LPBK Loopback Control. This bit enables the digital internal loopback from the ADC to the Front DAC. This feature is normally used for test and troubleshooting. 0 = No Loopback (Default) 1 = Loopback PCM digital data from ADC output to DAC See LBKS bit in Register 0x74 for changing the loopback path to use the Surround or Center/LFE DACs. MIC Select. Selects Mono MIC input. 0 = Select MIC1 1 = Select MIC2 See 2CMIC bit in Register 76h to enable stereo microphone recording. Double Rate Slot Select. The DRSS bits specify the slots for the n + 1 sample outputs. PCM L (n + 1) and PCM R (n + 1) data are by default provided in output slots 10 and 11. 00: PCM L, R n + 1 Data is on Slots 10, 11 (reset default) 01: PCM L, R n + 1 Data is on Slots 7, 8 10: Reserved 11: Reserved Audio Interrupt and Paging Mechanism Register (Index 24h) MS DRSS [1:0] Reg No. Name 24h Audio Interrupt and Paging D15 I4 D14 X D13 D12 X X D11 I0 D10 X D9 X D8 X D7 X D6 X D5 X D4 X D3 PG3 D2 PG2 D1 PG1 D0 Default PG0 xxxxh This register controls the Audio Interrupt and Paging mechanism. All registers not shown and bits containing an X are assumed to be reserved. PG[3:0] I0 Page Selector (Read Only). This register is used to describe Page Selector capability for extended features. Reading these bits returns 0h, which describes Page Selection as vendor specific only. INTERRUPT ENABLE (R/W). This enables interrupt generation. 0 = Interrupt Generation is Masked (Default) 1 = Interrupt Generation is Unmasked The S/W should not unmask the interrupt unless ensured by the AC '97 controller that no conflict is possible with Modem slot 12 GPI functionality. AC '97 2.2 compliant controllers will not likely support audio codec interrupt infrastructure. In that case, S/W could poll the interrupt status after initiating a sense cycle and waiting for Sense Cycle Max Delay to determine if an interrupting event has occurred. INTERRUPT STATUS (R/W). This bit provides interrupt status and clear capability. 0 = Interrupt is Clear 1 = Interrupt was Generated Interrupt event is cleared by writing a "1" to this bit. The interrupt bit will change regardless of condition of interrupt enable (I0) status. An interrupt in the GPI in slot 12 in the AC link will follow this bit change when interrupt enable (I0) is unmasked. I4 -16- REV. 0 AD1980 Power-Down Control/Status Register (Index 26h) Reg No. Name 26h Power-Down Control/Status D15 EAPD D14 PR6 D13 D12 PR5 PR4 D11 PR3 D10 PR2 D9 PR1 D8 PR0 D7 X D6 X D5 X D4 X D3 REF D2 D1 D0 Default ANL DAC ADC NA The ready bits are read only; writing to REF, ANL, DAC, ADC will have no effect. These bits indicate the status for the AD1980 subsections. If the bit is a 1, then that subsection is ready. Ready is defined as the subsection able to perform in its nominal state. All registers not shown and bits containing an X are assumed to be reserved. ADC DAC ANL REF PR[6:0] ADC Sections Ready to Transmit Data DAC Sections Ready to Transmit Data Analog Amplifiers, Attenuators and Mixers Ready Voltage References, VREF and VREFOUT up to Nominal Level Codec Power-Down Modes. The first three bits are to be used individually rather than in combination with each other. PR3 can be used in combination with PR2 or by itself. The mixer and reference cannot be powered down via PR3 unless the ADCs and DACs are also powered down. Nothing else can be powered up until the reference is up. PR5 has no effect unless all ADCs, DACs, and the AC-Link are powered down. The reference and the mixer can be either up or down, but all power-up sequences must be allowed to run to completion before PR5 and PR4 are both set. In multiple codec systems, the master codec's PR5 and PR4 bits control the slave codec. PR5 is also effective in the slave codec if the master's PR5 bit is clear, but the PR4 bit has no effect except to enable or disable PR5. External Audio Power-Down Control. Controls the state of the EAPD pin. EAPD = 0 sets the EAPD pin low, enabling an external power amplifier (reset defaults). EAPD = 1 sets the EAPD pin high, shutting off the external power amplifier. EAPD REV. 0 -17- AD1980 PR0 = 1 PR1 = 1 PR2 = 1 PR4 = 1 NORMAL ADCs OFF PR0 DACs OFF PR1 ANALOG OFF PR2 OR PR3 DIGITAL I/F OFF PR4 SHUT OFF AC-LINK PR0 = 0 AND ADC = 1 PR1 = 0 AND DAC = 1 PR2 = 0 AND ANL = 1 WARM RESET READY = 1 DEFAULT COLD RESET Figure 8. One Example of AC `97 Power-Down/Power-Up Flow Extended Audio ID Register (Index 28h) Reg No. Name 28h Ext'd Audio D15 D14 D13 D12 D11 ID1 ID0 X X D10 D9 D8 D7 D6 D5 DSA1 D4 DSA0 D3 D2 X D1 D0 Default X3C7h REV1 REV0 AMAP LDAC SDAC CDAC SPDIF DRA VRA The extended audio ID register identifies which extended audio features are supported. A nonzero extended audio ID value indicates one or more of the extended audio features are supported. All registers not shown and bits containing an X are assumed to be reserved. VRA DRA Variable Rate PCM Audio Support (Read Only). This bit returns a "1" when read to indicate that the Variable Rate PCM Audio is supported. Double Rate Audio (Read Only). This bit returns a "1" when read to indicate that the optional Double Rate RCM Audio is supported for PCM L and PCM R. SPDIF Support (Read Only). This bit returns a "1" when read to indicate that the SPDIF transmitter is supported (IEC958). This bit is also used to validate that the SPDIF transmitter output is actually enabled. The SPDIF bit is only allowed to be set high if the SPDIF pin (48) is pulled down at power-up, enabling the codec transmitter logic. If the SPDIF pin is floating or pulled high at power-up, the transmitter logic is disabled and therefore this bit returns a low, indicating that the SPDIF transmitter is not available. This bit must always be read back to verify that the SPDIF transmitter is actually enabled. DAC Slot Assignments (Read/Write) (Reset Default = 00) 00 DACs 1, 2 = 3 and 4 DACs 3, 4 = 7 and 8 DACs 5, 6 = 6 and 9 01 DACs 1, 2 = 7 and 8 DACs 3, 4 = 6 and 9 DACs 5, 6 = disabled 10 DACs 1, 2 = 6 and 9 DACs 3, 4 = disabled DACs 5, 6 = disabled 11 Reserved PCM CENTER DAC Support (Read Only). This bit returns a "1" when read to indicate that PCM center DAC is supported. PCM Surround DAC Support (Read Only). This bit returns a "1" when read to indicate that PCM surround left and right DACs are supported. PCM LFE DAC Support (Read Only), This bit returns a "1" when read to indicate that PCM LFE DAC is supported. Slot DAC Mappings Based on Codec ID (Read Only). This bit returns a "1" when read to indicate that slot/DAC mappings based on codec ID are supported. REV[1,0] = 01 indicates codec is AC '97 revision 2.2 compliant (Read Only). Indicates Codec Configuration (Read Only). 00 = Primary 01, 10, 11 = Secondary SPDIF DSA[1,0] CDAC SDAC LDAC AMAP REV[1,0] ID[1:0] -18- REV. 0 AD1980 Extended Audio Status and Control Register (Index 2Ah) Reg No. Name D15 D14 D13 D12 D11 D10 PRK PRJ D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default 2Ah Extended Audio VFORCE X Stat/Ctrl PRI SPCV X ELDAC ESDAC ECDAC SPSA1 SPSA0 X ESPDIF EDRA EVRA 0XX0h The extended audio status and control register is a read/write register that provides status and control of the extended audio features. All registers not shown and bits containing an X are assumed to be reserved. EVRA Variable Rate Audio (Read/Write). VRA = 0, sets fixed sample rate audio at 48 kHz (Reset Default). VRA = 1, enables variable rate audio mode (enables sample rate registers and SLOTREQ signaling). Double Rate Audio. DRA = 1 enables double rate audio mode in which data from PCM L and PCM R in output slots 3 and 4 is used in conjunction with PCM L (n + 1) and PCM R (n + 1) data to provide DAC streams at twice the sample rate designated by the PCM front sample rate control register. When using the double rate audio only the front DACs are supported, and all other DACs (surround, center, and LFE) are automatically powered down. Note that DRA can be used without VRA; in that case the converter rates are forced to 96 kHz if DRA = 1. SPDIF Transmitter Subsystem Enable/Disable Bit (Read/Write). SPDIF = 1 enables the SPDIF transmitter. SPDIF = 0 disables the SPDIF transmitter (default). SPDIF Slot Assignment Bits (Read/Write). These bits control the SPDIF slot assignment and respective defaults, depending on the codec ID configuration. See the following table. Center DAC Status (Read Only). CDAC = 1 indicates the PCM center DAC is ready. Surround DAC status (Read Only). SDAC = 1 indicates the PCM surround DACs are ready. LFE DAC status (Read Only). LDAC = 1 indicates the PCM LFE DAC is ready. SPDIF Configuration Valid (Read Only). Indicates the status of the SPDIF transmitter subsystem, enabling the driver to determine if the currently programmed SPDIF configuration is supported. SPCV is always valid, independent of the SPDIF enable bit status. SPCV = 0 indicates current SPDIF configuration (SPSA, SPSR, DAC slot rate, DRS) is not valid (not supported). SPCV = 1 indicates current SPDIF configuration (SPSA, SPSR, DAC slot rate, DRS) is valid (supported). Center DAC Power-Down (Read/Write). PRJ = 1 turns off the PCM Center DAC. Surround DACs Power-Down (Read/Write). PRJ = 1 turns off the PCM surround DACs. LFE DAC Power-Down (Read/Write). PRJ = 1 turns off the PCM LFE DAC. Validity Force Bit (Reset Default = 0). When asserted, this bit forces the SPDIF stream validity flag (Bit 28 within each SPDIF L/R subframe) to be controlled by the V bit (D15) in Register 3Ah (SPDIF control register). VFORCE = 0 and V = 0; the Validity Bit is managed by the codec error detection logic. VFORCE = 0 and V = 1; the Validity Bit is forced high, indicating subframe data is invalid. VFORCE = 1 and V = 0; the Validity Bit is forced low, indicating subframe data is valid. VFORCE = 1 and V = 1; the Validity Bit is forced high, indicating subframe data is invalid. EDRA ESPDIF SPSA[1,0] ECDAC ESDAC ELDAC SPCV PRI PRJ PRK VFORCE REV. 0 -19- AD1980 AC '97 2.2 AMAP Compliant Default SPDIF Slot Assignments Codec ID 00 00 00 01 01 10 10 11 Function 2-Ch Primary w/SPDIF 4-Ch Primary w/SPDIF 6-Ch Primary w/SPDIF +2-Ch Secondary w/SPDIF +4-Ch Secondary w/SPDIF +2-Ch Secondary w/SPDIF +4-Ch Secondary w/SPDIF +2-Ch Secondary w/SPDIF SPSA = 00 3 and 4 3 and 4 3 and 4 3 and 4 3 and 4 3 and 4 3 and 4 3 and 4 SPSA = 01 7 and 8 [default] 7 and 8 7 and 8 7 and 8 7 and 8 7 and 8 7 and 8 7 and 8 SPSA = 10 6 and 9 6 and 9[default] 6 and 9 6 and 9[default] 6 and 9 6 and 9[default] 6 and 9 6 and 9 SPSA = 11 10 and 11 10 and 11 10 and 11[default] 10 and 11[default] 10 and 11[default] 10 and 11[default] PCM Front DAC Rate Register (Index 2Ch) Reg No. Name 2Ch PCM Front DAC Rate D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default SRF15 SRF14 SRF13 SRF12 SRF11 SRF10 SRF9 SRF8 SRF7 SRF6 SRF5 SRF4 SRF3 SRF2 SRF1 SRF0 BB80h This read/write Sample Rate Control Register contains 16-bit unsigned value, representing the rate of operation in Hz. SRF[15:0] Sample Rate. The sampling frequency range is from 7 kHz (1B58h) to 48 kHz (BB80h) in 1 Hz increments. If zero is written to VRA, then the sample rate is reset to 48 kHz. PCM Surround DAC Rate Register (Index 2Eh) Reg No. Name 2Eh PCM Surr DAC Rate D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default SRS15 SRS14 SRS13 SRS12 SRS11 SRS10 SRS9 SRS8 SRS7 SRS6 SRS5 SRS4 SRS3 SRS2 SRS1 SRS0 BB80h This read/write Sample Rate Control Register contains 16-bit unsigned value, representing the rate of operation in Hz. This register sets the sample rate for the surround DAC. This register's reset default is to be locked to the PCM front DAC sample rate register (2-Ch). To unlock this register, Bit SRU in Register 76h must be asserted. SRS[15:0] Sample Rate. The sampling frequency range is from 7 kHz (1B58h) to 48 kHz (BB80h) in 1 Hz increments. If zero is written to VRA bit, then the sample rate is reset to 48 kHz. PCM LFE (and CENTER) DAC Rate Register (Index 30h) Reg No. Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default 30h PCM LFE/ SRCL15 SRCL14 SRCL13 SRCL12 SRCL11 SRCL10 SRCL9 SRCL8 SRCL7 SRCL6 SRCL5 SRCL4 SRCL3 SRCL2 SRCL1 SRCL0 BB80h C DAC Rate This read/write sample rate control register contains 16-bit unsigned value, representing the rate of operation in Hz. This register sets the sample rate for the LFE DAC and Center DAC. This register's reset default is to be locked to the PCM Front DAC sample rate register (2-Ch) . To unlock the register bit, SRU in Register 76h must be asserted. SRCL[15:0] Sample Rate. The sampling frequency range is from 7 kHz (1B58h) to 48 kHz (BB80h) in 1 Hz increments. If zero is written to VRA, then the sample rate is reset to 48 kHz. PCM ADC Rate Register (Index 32h) Reg No. Name 32h PCM L/R ADC Rate D15 SRA15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default SRA14 SRA13 SRA12 SRA11 SRA10 SRA9 SRA8 SRA7 SRA6 SRA5 SRA4 SRA3 SRA2 SRA1 SRA0 BB80h This read/write sample rate control register contains 16-bit unsigned value, representing the rate of operation in Hz. SRA[15:0] Sample Rate. The sampling frequency range is from 7 kHz (1B58h) to 48 kHz (BB80h) in 1 Hz increments. If zero is written to VRA, then the sample rate is reset to 48 kHz. -20- REV. 0 AD1980 CENTER/LFE Volume Control Register (Index 36h) Reg No. Name D15 D14 X D13* D12 D11 D10 D9 D8 D7 D6 D5* X D4 D3 D2 D1 D0 Default 36h Center/LFE LM Volume LFE5 LFE4 LFE3 LFE2 LFE1 LFE0 CM CNT5 CNT4 CNT3 CNT2 CNT1 CNT0 8080h All registers not shown and bits containing an X are assumed to be reserved. Refer to Table VII for examples. This register controls the LFE output volume and mute bit. The volume registers contain five bit, generating 32 volume levels with 31 steps of 1.5 dB each. If MSPLT is not set, Bit D7 has no effect. *Because AC '97 defines 6-bit volume registers, to maintain compatibility, whenever the D5 or D13 bit is set to "1," its respective lower five volume bits are automatically set to "1" by the codec logic. On readback, all lower five bits will read "1"s whenever this bit is set to "1." Note that depending on the state of the AC97NC bit in register 76h, this register operates as follows: For AC97NC = 0, the register controls the center and LFE output pin Attenuators. Range is 0 dB to -46.5 dB. For AC97NC = 1, the register controls the center and LFE DAC Gain/Attenuators. Range is +12 dB to -34.5 dB. CNT[5:0] CM LFE[5:0] LM Center Volume Control Center Volume Mute. When this bit is set to "1," the channel is muted. LFE Volume Control LFE Volume Mute. When this bit is set to "1," the channel is muted. Table VII. Settings for Center/LFE Register Control Bits CENTER and LFE Volume (36h) D15/D7 0 0 0 0 1 CENTER D[5:0] and LFE D[13:8] WRITE READBACK 00 0000 00 1111 01 1111 1x xxxx xx xxxx 00 0000 00 1111 01 1111 01 1111 xx xxxx Function with AC97NC = 0 0 dB Gain -22 dB Gain -46.5 dB Gain -46.5 dB Gain Muted Function with AC97NC = 1 12 dB Gain -10.5 dB Gain -34.5 dB Gain Not Applicable Muted Surround Volume Control Register (Index 38h) Reg No. 38h Name Surround Volume D15 D14 D13* D12 D11 D10 D9 D8 D7 D6 D5* D4 D3 D2 D1 D0 Default MUTE_L X LSR5 LSR4 LSR3 LSR2 LSR1 LSR0 MUTE_R X RSR5 RSR4 RSR3 RSR2 RSR1 RSR0 8080h *Refer to Table VIII for examples. This register controls the surround volume controls for both stereo channels and mute bits. Each volume subregister contains five bits, generating 32 volume levels with 31 steps of 1.5 dB each. Because AC '97 defines 6-bit volume registers, to maintain compatibility, whenever the D5 or D13 Bit is set to 1, its respective lower five volume bits are automatically set to "1" by the coded logic. On readback , all lower five bits will read "1s" whenever these bits are set to "1." Note that depending on the state of the AC97NC bit in Register 0x76, this register operates as follows: For AC97NC = 0, the register controls the surround output pin Attenuators. Range is 0 dB to -46.5 dB. For AC97NC = 1, the register controls the surround DAC Gain/Attenuators. Range is +12 dB to -34.5 dB. RSR[5:0] MUTE_R LSR[5:0] MUTE_L Right Surround Volume Control Right Surround Volume Mute. When this bit is set to "1," the right channel is muted. Left Surround Volume Control Left Surround Volume Mute. When this bit is set to "1," the left channel is muted. REV. 0 -21- AD1980 Table VIII. Settings for Surround Register Control Bits Surround Volume (38h) Left Surround D[13:8] Right Surround D[5:0] WRITE READBACK 00 0000 00 0000 00 1111 00 1111 01 1111 01 1111 1x xxxx 01 1111 xx xxxx xx xxxx D15/D7 0 0 0 0 1 Function with AC97NC = 0 0 dB Gain -22 dB Gain -46.5 dB Gain -46.5 dB Gain Muted Function with AC97NC = 1 12 dB Gain -10.5 dB Gain -34.5 dB Gain Not Applicable Muted SPDIF Control Register (Index 3Ah) Reg No. Name 3Ah SPDIF Control D15 V D14 X D13 SPSR1 D12 SPSR0 D11 L D10 CC6 D9 D8 D7 CC3 D6 CC2 D5 CC1 D4 CC0 D3 D2 D1 D0 Default CC5 CC4 PRE COPY /AUD PRO 2000h All registers not shown and bits containing an X are assumed to be reserved. Register 3Ah is a read/write register that controls SPDIF functionality and manages bit fields propagated as channel status (or subframe in the V case). With the exception of V, this register should only be written to when the SPDIF transmitter is disabled (SPDIF Bit in Register 2Ah is "0"). This ensures that control and status information starts up correctly at the beginning of SPDIF transmission. PRO /AUD COPY PRE CC[6-0] L SPSR[1,0] Professional. "1" indicates professional use of channel status, "0" indicates consumer. Non-Audio. "1" indicates data is non PCM format, "0" indicates data is PCM. Copyright. "1" indicates copyright is asserted, "1" indicates copyright is not asserted. Pre-emphasis. "1" indicates filter pre-emphasis is 50 s/15 s, "0" indicates pre-emphasis is none. Category Code. Programmed according to IEC standards, or as appropriate. Generation Level. Programmed according to IEC standards, or as appropriate. SPDIF Transmit Sample Rate: SPSR[1:0] = "00" Transmit Sample Rate = 44.1 kHz SPSR[1:0] = "01" Reserved SPSR[1:0] = "10" Transmit Sample Rate = 48 kHz (default) SPSR[1:0] = "11" Not supported. Validity. This bit affects the Validity flag (Bit 28 transmitted in each SPDIF L/R subframe) and enables the SPDIF transmitter to maintain connection during error or mute conditions. V = 1 Each SPDIF subframe (L+R) has Bit 28 set to "1." This tags both samples as invalid. V = 0 Each SPDIF subframe (L+R) has Bit 28 set to "0" for valid data and "1" for invalid data (error condition). Note that when V = 0, asserting the VFORCE bit (D15) in Register 2Ah (Ext'd Audio Stat/Ctrl) will force the Validity flag low, marking both samples as valid. V -22- REV. 0 AD1980 EQ Control Register (Index 60h) Reg No. Name D15 D14 X D13 X D12 X D11 X D10 X D9 X D8 X D7 D6 D5 D4 D3 D2 D1 D0 Default 60h EQ CTRL EQM SYM CHS BCA5 BCA4 BCA3 BCA2 BCA1 BCA0 8080h All registers not shown, and bits containing an X are assumed to be reserved. Register 60h is a read/write register that controls the Equalizer functionality and data setup. This register also contains the Biquad and Coefficient Address pointer, which is used in conjunction with the EQ Data Register (78h) to set up the equalizer coefficients. The reset default disables the Equalizer function until the coefficients can be properly set up by the software and sets the Symmetry Bit to allow equal coefficients for the left and right channels. BCA[5,0] Biquad and Coefficient Address Pointer: biquad 0 biquad 0 biquad 0 biquad 0 biquad 0 biquad 1 biquad 1 biquad 1 biquad 1 biquad 1 biquad 2 biquad 2 biquad 2 biquad 2 biquad 2 biquad 3 biquad 3 biquad 3 biquad 3 biquad 3 biquad 4 biquad 4 biquad 4 biquad 4 biquad 4 biquad 5 biquad 5 biquad 5 biquad 5 biquad 5 biquad 6 biquad 6 biquad 6 biquad 6 biquad 6 coef a0 coef a1 coef a2 coef b1 coef b2 coef a0 coef a1 coef a2 coef b1 coef b2 coef a0 coef a1 coef a2 coef b1 coef b2 coef a0 coef a1 coef a2 coef b1 coef b2 coef a0 coef a1 coef a2 coef b1 coef b2 coef a0 coef a1 coef a2 coef b1 coef b2 coef a0 coef a1 coef a2 coef b1 coef b2 BCA[5,0] = 011011 BCA[5,0] = 011010 BCA[5,0] = 011001 BCA[5,0] = 011101 BCA[5,0] = 011100 BCA[5,0] = 100000 BCA[5,0] = 011111 BCA[5,0] = 011110 BCA[5,0] = 100010 BCA[5,0] = 100001 BCA[5,0] = 100101 BCA[5,0] = 100100 BCA[5,0] = 100011 BCA[5,0] = 100111 BCA[5,0] = 100110 BCA[5,0] = 101010 BCA[5,0] = 101001 BCA[5,0] = 101000 BCA[5,0] = 101100 BCA[5,0] = 101011 BCA[5,0] = 101111 BCA[5,0] = 101110 BCA[5,0] = 101101 BCA[5,0] = 110001 BCA[5,0] = 110000 BCA[5,0] = 110100 BCA[5,0] = 110011 BCA[5,0] = 110010 BCA[5,0] = 110110 BCA[5,0] = 110101 BCA[5,0] = 111001 BCA[5,0] = 111000 BCA[5,0] = 110111 BCA[5,0] = 111011 BCA[5,0] = 111010 CHS Channel Select. CHS = 0 selects left channel coefficients data block. CHS = 1 selects right channel coefficients data block. Symmetry. When set to "1," this bit indicates that the left and right channel coefficients are equal. This shortens the coefficients' setup sequence since only the left channel coefficients need to be addressed and set up. (The right channel coefficients are fetched from the left channel memory.) Equalizer Mute. When set to "1," this bit disables the equalizer function (allows all data pass through). The reset default sets this bit to "1," disabling the equalizer function until the biquad coefficients can be properly set. SYM EQM REV. 0 -23- AD1980 EQ Data Register (Index 62h) Reg No. Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default 62h EQ DATA CFD15 CFD14 CFD13 CFD12 CFD11 CFD10 CFD9 CFD8 CFD7 CFD6 CFD5 CFD4 CFD3 CFD2 CFD1 CFD0 0000h This read/write register is used to transfer EQ biquad coefficients into memory. The register data is transferred to, or retrieved from, the address pointed to by the BCA Bits in the EQ CNTRL register (60h). Data will only be written to memory if the EQM bit (Register 60h, Bit 15) is asserted. CFD[15,0] Coefficient Data. The biquad coefficients are fixed-point format values with 16 bits of resolution. The CFD15 bit is the MSB and the CFD0 bit is the LSB. Jack Sense/Audio Interrupt Status Register (Index 72h) Reg No. Name 72h Jack Sense D15 D14 D13 D12 D11 JS MT1 D10 JS MT0 D9 JS1 EQB D8 JS0 EQB D7 JS1 TMR D6 JS0 TMR D5 JS1 MD D4 JS0 MD D3 JS1 ST D2 JS0 ST D1 JS1 INT D0 JS0 INT Default 0000h JS1 JS1 JS0 JS SPRD DMX DMX MT2 All register bits are read/write except for JS0ST and JS1ST, which are read only. JS0INT Indicates Pin JS0 has generated an interrupt. Remains set until the software services JS0 interrupt, i.e., JS0 ISR should clear this bit by writing a "0" to it. Note that the interrupt to the system is actually an OR combination of this bit and JS1INT. Also, note that the actual interrupt implementation is selected by the INTS bit (Register 76h). It is also possible to generate a software system interrupt by writing a "1" to this bit. Indicates Pin JS1 has generated an interrupt. Remains set until the software services JS1 interrupt, i.e., JS1 ISR should clear this bit by writing a "0" to it. See the JS0INT description for additional details. JS0 STATE. This bit always reports the logic state of JS0 pin. JS1 STATE. This bit always reports the logic state of JS1 pin. JS0 Mode. This bit selects the operation mode for the JS0 pin. 0 = Jack Sense Mode (reset default) 1 = Interrupt Mode JS1 Mode. This bit selects the operation mode for the JS1 pin. 0 = Jack Sense Mode (reset default) 1 = Interrupt Mode JS0 Timer Enable. If this bit is set to a "1," JS0 must be high for greater than 278 ms to be recognized. JS1 Timer Enable. If this bit is set to a "1," JS1 must be high for greater than 278 ms to be recognized. JS0 EQ Bypass Enable. This bit enables JS0 to control the EQ bypass. When this bit is set to "1," JS0 = 1 will cause the EQ to be bypassed. JS1 EQ Bypass Enable. This bit enables JS1 to control the EQ bypass. When this bit is set to "1," JS1 = 1 will cause the EQ to be bypassed. JS Mute Enable Selector. These three bits select and enable the Jack Sense muting action (see Table IX). JS0 Down = Mix Control Enable. This bit enables JS0 to control the Down-Mix function. This function allows a digital mix of six channels of audio into 2-channel audio. The mix can then be routed to the stereo Line_out or HP_out jacks. When this bit is set to "1," JS0 = 1 will activate the Down-Mix conversion. See the DMIX description in Register 76h. The DMIX bits select the Down-Mix implementation type and can also force the function to be activated. JS1 Down Mix Control Enable. This bit enables 2-channel to 6-channel audio Spread function when both Jack Senses are active (logic state "1"). Note that the SPRD bit can also force the Spread function without being gated by the Jack Senses. See this bit's description in Register 76h for a better understanding of the Spread function. JS Spread Control Enable. This bit enables 2-channel to 6-channel audio Spread function when both Jack Senses are active (logic state "1"). Note that the SPRD bit can also force the Spread function without being gated by the Jack Senses. See this bit's description in Register 76h for a better understanding of the Spread function. -24- REV. 0 JS1INT JS0ST JS1ST JS0MD JS1MD JS0TMR JS1TMR JS0EQB JS1EQB JSMT[2,0] JS0DMX JS1DMX JSSPRD AD1980 Table IX. Jack Sense Mute Select (JSMT [2:0]) REF 0 1 2 3 4 5 6 7 JS1 OUT OUT IN IN OUT OUT IN IN (0) (0) (1) (1) (0) (0) (1) (1) JS0 OUT IN OUT IN OUT IN OUT IN (0) (1) (0) (1) (0) (1) (0) (1) HP JSMT2 JSMT1 JSMT0 OUT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE LINE OUT ACTIVE ACTIVE ACTIVE ACTIVE FMUTE FMUTE ACTIVE ACTIVE C/LFE OUT ACTIVE ACTIVE ACTIVE ACTIVE FMUTE FMUTE ACTIVE ACTIVE MONO OUT ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE NOTES JS0 and JS1 ignored JS0 no mute action, JS1 mutes mono and enables LINE_OUT and C/LFE. Standard 6-channel config swapped HP_OUT and LINE_OUT. JS0 no mute action, JS1 mutes Mono and enables HP_OUT and C/LFE. Standard 6-channel config no swap. ** Reserved 8 9 10 11 OUT OUT IN IN (0) (0) (1) (1) OUT IN OUT IN (0) (1) (0) (1) 0 0 0 0 1 1 1 1 0 0 0 0 FMUTE FMUTE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE FMUTE FMUTE ACTIVE ACTIVE ACTIVE ACTIVE FMUTE FMUTE 12 13 14 15 16 17 18 19 OUT OUT IN IN OUT OUT IN IN (0) (0) (1) (1) (0) (0) (1) (1) OUT IN OUT IN OUT IN OUT IN (0) (1) (0) (1) (0) (1) (0) (1) 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 ** ** ** ** ACTIVE ACTIVE ACTIVE ACTIVE ** ** ** ** FMUTE ACTIVE FMUTE FMUTE ** ** ** ** FMUTE ACTIVE FMUTE FMUTE ** ** ** ** ACTIVE FMUTE FMUTE FMUTE JS0 = 0 and JS1 = 0 enables mono. JS1 = 1 enables front only. JS0 = 1 enables all rear. 6-chan config with front jack wrap back. JS0 no mute action, JS1 mutes mono and enables LINE_OUT + HP_OUT + C/LFE. Standard 6-channel config swapped HP_OUT and LINE_OUT. ** Reserved 20 21 22 23 OUT OUT IN IN (0) (0) (1) (1) OUT IN OUT IN (0) (1) (0) (1) 1 1 1 1 0 0 0 0 1 1 1 1 FMUTE FMUTE ACTIVE ACTIVE FMUTE FMUTE ACTIVE ACTIVE FMUTE FMUTE ACTIVE ACTIVE ACTIVE FMUTE FMUTE FMUTE 24 25 26 27 28 29 30 31 OUT OUT IN IN OUT OUT IN IN (0) (0) (1) (1) (0) (0) (1) (1) OUT IN OUT IN OUT IN OUT IN (0) (1) (0) (1) (0) (1) (0) (1) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** Reserved FMUTE = Output is forced to mute independent of the respective Volume Register setting. ACTIVE = Output is not muted and its status is dependent on the respective Volume Register setting. OUT = Nothing plugged into the jack and therefore the JS status is "0" (via the load resistor pull-down). IN = Jack has plug inserted and therefore the JS status is "1" (via the codec JS internal pull-up). REV. 0 -25- AD1980 Serial Configuration Register (Index 74h) Reg No. Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default 74h Serial SLOT16 REGM2 REGM1 REGM0 REGM3 DRF X Configuration CHEN X LBKS1 LBKS0 INTS X SPAL SPDZ SPLNK 1001h All registers not shown and bits containing an X are assumed to be reserved. Note that this register is not reset when the reset register (0x00) is written to (soft reset). SPLNK SPDIF Link. This bit enables the SPDIF to link with the front DACs for data requesting. 0 = SPDIF and DAC are not linked. 1 = SPDIF and DAC are linked and receive the same data requests (reset default). SPDIF DACZ. 0 = Repeat last sample out of the SPDIF stream if FIFO under-runs (reset default). 1 = Forces midscale sample out the SPDIF stream if FIFO under-runs. SPDIF ADC Loop-around. 0 = SPDIF transmitter is connected to the AC-Link stream (reset default). 1= SPDIF transmitter is connected to the digital ADC stream, not the AC-Link. Interrupt Mode Select. This bit selects the JS interrupt implementation path. 0 = Bit 0 SLOT 12 (modem interrupt) (reset default). 1 = Slot 6 Valid Bit (MIC ADC interrupt). Loop-Back Selection. These bits select the internal digital loop-back path when LPBK bit is active (see Register 20h) 00 = Loop back through the front DACs (reset default). 01 = Loop back through the surround DACs. 10 = Reserved 11 = Loop-back through the center and LFE DACs (Center DAC loops back from the ADC left channel, the LFE DAC from the ADC right channel). Chain Enable. This bit enables chaining of a slave codec SDATA_IN stream into the ID0 pin (Pin 45). 0 = Disable chaining (reset default). 1 = Enable chaining into ID0 pin. DAC Request Force. This allows the AD1980 to synchronize DAC requests with the AD1981A/B. 0 = Normal DAC requesting sequence (reset default). 1 = Synchronize to AD1981A/B DAC requests. Slave 3 Codec Register Mask Master Codec Register Mask Slave 1 Codec Register Mask Slave 2 Codec Register Mask Enable 16-Bit Slot Mode. SLOT16 makes all ac-link slots 16 bits in length, formatted into 16 slots. This is a preferred mode for DSP serial port interfacing. SPDZ SPAL INTS LBKS[1:0] CHEN DRF REGM3 REGM0 REGM1 REGM2 SLOT16 -26- REV. 0 AD1980 Miscellaneous Control Bit Register (Index 76h) Reg No. Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default 76th Misc DACZ AC97NC MSPLT LODIS CLDIS HPSEL DMIX1 DMIX0 SPRD 2CMIC LOSEL SRU VREFH VREFD MBG1MBG0 0000h Control Bits MBG[1:0] MIC Boost Gain Select Register. These two bits allow changing the MIC preamp gain from the nominal 20 dB gain. Both MIC1/MIC2 and MIC2 preamps will be set to the same selected gain. Note that this gain takes effect only while Bit D6 (M20) on the MIC volume register (0Eh) is set to 1; otherwise the MIC boost block has a gain of 0 dB. 00 = 20 dB gain (reset default) 01 = 10 dB gain 10 = 30 dB gain 11 = reserved VREFOUT Disable. Disables VREFOUT, placing it into High Z out mode. Note that this bit overrides the VREFH bit selection (see below). 0 = VREFOUT pin is driven by the internal reference (reset default). 1 = VREFOUT pin is placed into High Z out mode. VREFOUT High. Changes VREFOUT from 2.25 V to 3.70 V for PC2001 compliant MIC bias applications. 0 = VREFOUT pin is set to 2.25 V output (reset default). 1 = VREFOUT pin is set to 3.70 V output. Sample Rate Unlock. Controls DAC sample rate locking. 0 = All DAC Sample Rates are locked to the front sample rate (reset default). 1 = DAC sample rates can be set independently for front, surround, and LFE. LINE_OUT Amplifiers Input Select. This bit allows the LINE_OUT output amplifiers to be driven by the mixer or the surround DACs. The main purpose for this is to allow swapping of the front and surround channels to make better use of the SURR/HP_OUT output amplifiers. This bit should normally be used in tandem with the HPSEL bit (see below). 0 = LINE_OUT amplifiers are driven by the mixer outputs (reset default). 1 = LINE_OUT amplifiers are driven by the surround DAC outputs. 2-Channel MIC Select. This bit enables simultaneous recording from MIC1 and MIC2 inputs, using a stereo microphone array. Note that this register works in conjunction with the MS bit in Register 20h. 0 = MIC1 or MIC2 (determined by MS bit) is routed to the record selector's left and right MIC channels as well as to the mixer (reset default). 1 = MIC1 is routed to the record selector's left MIC channel and MIC2 is routed to the record selector's right MIC channel. Note that in this mode, the MS bit should be set low and MIC1 can still be enabled into the mixer. SPREAD Enable. This bit enables spreading of 2-channel media to all six output channels. This function is implemented in the analog section by using the output selector controls line for the center/LFE, surround, and Line_out output channels. Note that the Jack Sense pins can also be set up to control (gate) this function, depending on the JSSPRD bit (see Register 72h). 0 = No spreading occurs unless activated by the Jack Senses and JSSPRD bits (reset default). 1 = The SPRD selector drives the center and LFE outputs from the MONO_OUT, the HPSEL selector drives the SURR/HP_OUT outputs from the mixer outputs, and the LOSEL selector drives the LINE_OUT outputs also from the mixer outputs. Note that the SPRD bit overrides the current output selector control lines set up by bits LOSEL and HPSEL as follows: LOSEL = 0 and HPSEL = 1. VREFD VREFH SRU LOSEL 2CMIC SPRD REV. 0 -27- AD1980 DMIX[1:0] Down Mix Mode Select. Provides analog down-mixing of the center, LFE, and/or surround channels into the mixer channels. This allows the full content of 5.1 or quad media to be played through stereo headphones or speakers. Note that the Jack Sense pins can also be set up to control (gate) this function depending on the JS0DMX and JS1DMX Bits (see Register 72h). The upper bit allows forcing the down-mix function: DMIX[1] = 0, no down-mix unless activated by the Jack Sense and JSxDMX bits (default). DMIX[1] = 1, forces down-mix function. The lower bit selects the down-mix type: DMIX[0] = 0, selects 6-to-4 down-mix. The center and LFE channels are summed equally into the mixer left and right channels (default). DMIX[0] = 1, selects 6-to-2 down-mix. The surround left and right channels are summed into the mixer left and right channels. Default for DMIX[1:0] is "00." Headphone Amplifier Input Select. This bit allows the headphone power amps to be driven from the surround DACs or from the mixer outputs. There are two reasons for this: one is to allow 2-channel media to use the higher power headphone amplifiers available on the SURR/HP_OUT outputs; the other is to allow spreading of 2-channel media to the surround outputs. Together with the LOSEL bit (see above), this bit also provides for analog swapping of the mixer (front) and surround outputs. 0 = SURR_out/HP_out outputs are driven by the surround DACs (reset default). 1 = SURR_out/HP_out outputs are driven by the mixer outputs. Center and LFE Disable. Disables the center and LFE output pins, placing them into High-Z mode so that the assigned output audio jack(s) can be shared for MIC inputs or other functions. 0 = Center and LFE output pins have normal audio drive capability (reset default). 1 = Center and LFE output pins are placed into High-Z mode. Line_out Disable. Disables the Line_out pins (L/R), placing them into High-Z mode so that the assigned output audio jack can be shared for Line Input function. 0 = Line_out pins have normal audio drive capability (reset default). 1 = Line_out pins are placed into High-Z mode. Mute Split. Allows separate mute control bits for master, HP, Line_in, CD, PCM OUT, and record volume/gain control registers. 0 = Both left and right channel mutes are controlled by Bit D15 in the respective registers (reset default). 1 = Bit D15 affects only the left channel mute and Bit D7 affects only the right channel mute. AC '97 No Compatibility Mode. This bit allows the surround, center, and LFE volume control registers and output attenuators to operate in a more functional mode than defined by the AC97 2.2 spec. This is called ADI compatibility mode. In AC '97 compatibility mode, the DAC Gain/Attenuators for the surround, center, and LFE are controlled by Register 18h (PCM volume). The output pin attenuators for the surround are controlled by Register 38h, and the output pin attenuators for the center and LFE are controlled by Register 36h. In ADI compatibility mode, the Surround DAC Gain/Attenuators are controlled by Register 38h, and the Center/ LFE DAC are controlled by Register 36h. The output pin attenuators for Center/LFE are controlled by Register 02h (Master Volume), and the output pin attenuators for Surround are controlled by Register 04h. 0 = AC97 compatibility mode (reset default). 1 = ADI compatibility mode. DAC Zero-Fill. Determines DAC data fill under starved condition. 0 = DAC data is repeated when DACs are starved for data (reset default). 1 = DAC data is zero-filled when DACs are starved for data. HPSEL CLDIS LODIS MSPLT AC97NC DACZ -28- REV. 0 AD1980 Vendor ID Register (Index 7Ch-7Eh) Reg No. Name D15 D14 D13 F6 F5 D12 F4 D11 F3 D10 F2 D9 F1 D8 F0 D7 S7 D6 S6 D5 S5 D4 S4 D3 S3 D2 D1 D0 Default S2 S1 S0 4144h 7Ch Vendor ID1 F7 S[7:0] F[7:0] Reg No. Name This register is ASCII encoded to A. This register is ASCII encoded to D. D15 D14 D13 D12 D11 D10 D9 D8 D7 T5 T4 T3 T2 D6 D5 D4 D3 D2 D1 D0 Default 7Eh Vendor ID2 T7 T6 T[7:0] REV[7:0] T1 T0 REV7 REV6 REV5 REV4 REV3 REV2 REV1 REV0 5370h This register is ASCII encoded to S. This register is set to 70h identifying the AD1980. Codec ID and Clock Selection Table XTL_IN GND GND GND XTAL into XTL_IN CLK INPUT CLK INPUT CLK INPUT ID1# 0 0 1 1 0 0 1 IDO# 0 1 0 1 0 1 X Codec ID SECONDARY, ID = 3 SECONDARY, ID = 2 SECONDARY, ID = 1 PRIMARY, ID = 0 PRIMARY, ID = 0 PRIMARY, ID = 0 RESERVED Codec Clocking Source 12.288 MHz (BIT_CLK from Primary Codec) 12.288 MHz (BIT_CLK from Primary Codec) 12.288 MHz (BIT_CLK from Primary Codec) 24.576 MHz Local XTAL or External CLK 14.3181 MHz (External into XTL_IN) 48.00 MHz (External into XTL_IN) RESERVED Note that internally, the ID pins have weak pull-ups and are inverted. REV. 0 -29- AD1980 OUTLINE DIMENSIONS 48-Lead Plastic Quad Flatpack [LQFP] 1.4 mm Thick (ST-48) Dimensions shown in millimeters 1.60 MAX 0.75 0.60 0.45 PIN 1 INDICATOR 48 1 9.00 BSC 37 36 1.45 1.40 1.35 0.20 0.09 SEATING PLANE TOP VIEW (PINS DOWN) 7.00 BSC 0.15 0.05 SEATING PLANE 7 3.5 0 0.08 MAX COPLANARITY VIEW A 12 13 24 25 VIEW A ROTATED 90 CCW 0.50 BSC 0.27 0.22 0.17 COMPLIANT TO JEDEC STANDARDS MS-026BBC -30- REV. 0 -31- -32- C03231-0-11/02(0) PRINTED IN U.S.A. |
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